The present invention relates to an integrated circuit, and more particularly to an integrated circuit for supplying a favorable signal to a group of circuits having the same input impedance.
For example, a flash analog-digital converter includes a plurality of circuits having the same input impedance. In a case where the flash analog-digital converter has an 8-bit digital output, 2.sup.8 resistors are connected in series, to obtain 2.sup.8 reference voltage levels. When an input signal having a voltage level is applied to the analog-digital converter, 2.sup.8 reference voltage levels are simulaneously compared with the input signal by 2.sup.8 comparators. When an input signal having a voltage level of 0 V is applied to the analog-digital converter, the outputs of all the comparators are put to a low level. Now, let us consider a case where the maximum value of the reference voltage levels is 8 V, and an input signal having a voltage level of 5.05 V is applied to the analog-digital converter. In this case, the outputs of comparators corresponding to reference voltage levels lower than 5.05 V are all put to a high level, and the outputs of comparators corresponding to reference voltage levels greater than 5.05 V are all put to the low level. Further, two adjacent comparators are selected from 2.sup.8 comparators so that the output of one of the adjacent comparators takes the high level and the output of the other comparator takes the low level, to convert the input signal into a binary code with the aid of an encoder.
In such a flash analog-digital converter, a clock signal is applied to each comparator in the form of a differential input for the NPN transistors shown in FIG. 6, and each NPN transistor has input capacitance C.sub.i.
Further, there are the inductance and capacitance due to a wiring pattern from a clock driver to the comparators. Thus, as shown in FIG. 7, an LC circuit which is an equivalent circuit, is formed between the clock driver and the input part of each comparator. Accordingly, ringing is generated in a clock signal applied to each comparator, on the basis of parasitic impedance of the LC circuit. The ringing generates a conversion error.
In order to prevent such ringing, for example, a compensation method has been used which utilizes a resistor 30 as shown in FIG. 5, (Technical Report of the Institute of Electronics, Information and Communication Engineers of Japan, Vol. 84, No. 11, SSD84-12, pages 79 through 86).
According to the above method, as shown in FIG. 5, 2.sup.8 comparators applied with reference voltage levels of 1 to 2.sup.8 are arranged in two columns, and a resistor 30 is connected between output terminals of a clock driver 20 for sending out a complementary signal, to weaken the overshoot generated between the output terminals, thereby reducing ringing due to the overshoot.
Indeed the circuit of FIG. 5 pays attention to the reduction of ringing at the terminals for delivering the clock signal, but the circuit pays no attention to the waveform of the clock signal at the input terminal of each comparator. Hence, when a high-speed clock signal is applied to the LC circuit of FIG. 7, ringing is still generated in the clock signal applied to the input terminal of each comparator. Thus, the conversion error of analog digital converter is increased.